EPIX Offers NEW 4M12 COC40 Processing Board

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Accelerate from 0 to 550 MOPS with the touch of a computer key! Feel the power of the Model 12, along with twin C40s, as they capture and process with breathtaking speed. The TMS320C40 digital signal processor, from Texas Instruments, is now available for use with the 4MEG VIDEO Model 12. Installed on a dedicated processor board, C40 support is available in single and dual DSP configurations.

The C40 DSP
The TMS320C40 (C40) DSP is a 50 MHz (40 ns instruction cycle) 32 bit floating point processor. In addition to an embedded CPU, it has six DMA channels, a coprocessor dedicated to managing the DMA channels, and 1 gigabyte (1024 megabytes) of address space. The DMA coprocessor can simultaneously move data on six DMA channels throughout the memory map while the C40's CPU is dedicated to processing. Up to 11 operations per cycle can be executed, resulting in 275 MOPS (Million Operations Per Second) with data throughput of 320 megabytes per second!

The C40 Processing System
A C40 is a C40 . . . is a C40. The C40 DSPs on our COC40™ boards are the same as the C40s used by our competition. The major distinction (read "improvement") results from EPIX innovation. EPIX didn't merely add a C40 to the Model 12, we added a C40 processing system-a system of memories (see block diagram) and software support that places EPIX C40 processing power in a class by itself.

Global Memory
The left half of the block diagram represents the various components associated with the C40's Global Memory. Four megabytes of Image Memory can be read or written by either the C40 processor or the Model 12 imaging board.

A 32/16/8 Data Mux allows selection of word size-the number of bytes transferred between image memory and the C40. Operations which move blocks of data (such as image copy) receive data transfers of 4 bytes (32 bits) for maximum processing speed. Operations such as pixel additions or convolutions, can use 1 byte words for 8 bit pixels, or 2 byte words for 9-16 bit pixels.

The Address Mux switches address lines between the Model 12 and the C40, and supports the different modes of the C40.

Local Memory
The right half of the block diagram represents the various components associated with the C40's Local Memory. The 256K x 32 bit Static Ram provides 1 megabyte of zero wait state memory for user-written programs and image cache. The Dual Port Static Ram provides 16KB of zero wait state memory for communication and control between the C40 processor and the PC bus.

Benchmarks
With the C40's short cycle time, parallel instructions, zero-overhead loops, and DMA capabilities (along with the various memories provided on the COC40 board), image processing operations can be performed very quickly. Complement operations require only 0.09 microseconds per pixel, and a 3x3 convolution only 1.23 microseconds per pixel!

COC402^TM Dual Processor Board
The block diagram, descriptions of the C40 processing system, and benchmarks, describe the capabilities of the COC40 processor board pictured on page 1. You'll notice a vast expanse of empty landscape -- 50% of the board is unpopulated. Imagine filling the empty space with a duplicate, independently controlled, C40 system. This board, the COC402, is in development.

Two C40 systems allow simultaneous capture and processing capability using 2 image memories, 4 megabytes each. While the first C40 is processing an image captured in its image memory, the second C40 is free to access image data, process, or save within its own dedicated bus system. While the first DSP is processing, the 4MEG VIDEO Model 12 can capture a new image and transfer it to the image memory of the second C40. The second C40 can execute an independent processing algorithm without regard to what the first C40 might be doing. Two C40s offer the potential to double processing throughput.

Symbolic Debugger
Included in 4MIP Version 2.9 is a complete symbolic debugger for assistance in user-programming of the COC40. User programs can be written in either TI's "C" or TI's assembly code with the assistance of assembly macros provided by EPIX. 4MIP will load the user program and provide disassembly of program memory complete with user-defined symbols. The debugger provides access to all C40 registers and can view or alter their contents. Program memory can be read as either hexadecimal, decimal, signed decimal, floating point, or TI assembly code.

To assist in debugging, up to 14 break points can be set by address, with respect to the program counter, or with respect to user-defined symbols. Program operation can also be suspended when a set of conditions, involving register or image memory location, are satisfied. For example, a program can stop execution when the pixel at location 100,100 is less than 20 and C40 address register ARO is not equal to zero.

The debugger provides the ability to single step through a program, the on-screen display shows the current instruction as well as surrounding instructions. User programs can also print messages on the PC display using a C printf format.

Summary
The COC40 processor board allows the coupling of the Model 12's flexible interfacing capabilities with the enhanced processing power of the C40 DSP. Images can be captured and analyzed quickly-resulting in rapid or longer sequences that can translate into a more accurate view and analysis of real world events. The symbolic debugger, included with the purchase of 4MIP software, provides a convenient development environment that allows sophisticated program development with relative ease.

Specifications and prices subject to change without notice.

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